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head tail filter testing done

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abhishekpythons
2026-04-17 18:14:15 +05:30
parent e4b91625ea
commit a8e7c14f45
294 changed files with 209839 additions and 208687 deletions
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synthesis/syntmp/statusReport.html
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@@ -37,36 +37,36 @@
<td>403</td>
<td>0</td>
<td>-</td>
<td>02m:53s</td>
<td>04m:18s</td>
<td>-</td>
<td><font size="-1">4/15/2026</font><br/><font size="-2">10:47 PM</font></td>
<td><font size="-1">4/17/2026</font><br/><font size="-2">8:31 AM</font></td>
</tr>
<tr>
<td class="optionTitle"> (premap)</td><td>Complete</td>
<td>65</td>
<td>64</td>
<td>15</td>
<td>0</td>
<td>0m:13s</td>
<td>0m:13s</td>
<td>365MB</td>
<td><font size="-1">4/15/2026</font><br/><font size="-2">10:48 PM</font></td>
<td>0m:15s</td>
<td>0m:15s</td>
<td>366MB</td>
<td><font size="-1">4/17/2026</font><br/><font size="-2">8:31 AM</font></td>
</tr>
<tr>
<td class="optionTitle"> (fpga_mapper)</td><td>Complete</td>
<td>103</td>
<td>102</td>
<td>120</td>
<td>0</td>
<td>03m:51s</td>
<td>03m:54s</td>
<td>521MB</td>
<td><font size="-1">4/15/2026</font><br/><font size="-2">10:52 PM</font></td>
<td>03m:58s</td>
<td>04m:02s</td>
<td>564MB</td>
<td><font size="-1">4/17/2026</font><br/><font size="-2">8:36 AM</font></td>
</tr>
<tr>
<td class="optionTitle">Multi-srs Generator</td>
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>00m:03s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">4/15/2026</font><br/><font size="-2">10:47 PM</font></td> </tbody>
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>00m:03s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">4/17/2026</font><br/><font size="-2">8:31 AM</font></td> </tbody>
</table>
<br>
<table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
@@ -74,8 +74,8 @@
<tfoot> <tr> <td class="optionTitle" colspan="2"></td><td class="optionTitle" colspan="2"></td></tr>
</tfoot>
<tbody> <tr>
<td title ="Total Carry Cells used" class="optionTitle" align="left">Carry Cells</td> <td>2335</td>
<td title ="Total Sequential Cells used" class="optionTitle" align="left">Sequential Cells</td> <td>7316</td>
<td title ="Total Carry Cells used" class="optionTitle" align="left">Carry Cells</td> <td>2263</td>
<td title ="Total Sequential Cells used" class="optionTitle" align="left">Sequential Cells</td> <td>7208</td>
</tr>
<tr>
<td title ="Total DSP Blocks used" class="optionTitle" align="left">DSP Blocks
@@ -85,13 +85,13 @@
<tr>
<td title ="Total Global Clock Buffers used" class="optionTitle" align="left">Global Clock Buffers</td> <td>7</td>
<td title ="Total RAM1K20 used" class="optionTitle" align="left">RAM1K20
(v_ram)</td> <td>34</td>
(v_ram)</td> <td>36</td>
</tr>
<tr>
<td title ="Total RAM64x12 used" class="optionTitle" align="left">RAM64x12
(v_ram)</td> <td>11</td>
<td title ="Total LUTs used" class="optionTitle" align="left">LUTs
(total_luts)</td> <td>15992</td>
(total_luts)</td> <td>15852</td>
</tr>
</tbody>
@@ -103,14 +103,14 @@
<tbody>
<tr><th class="optionTitle" align= "left ">Clock Name</th><th class="optionTitle" align= "left ">Req Freq</th><th class="optionTitle" align= "left ">Est Freq</th><th class="optionTitle" align= "left ">Slack</th></tr>
<tr> <td align="left">COREJTAGDEBUG_Z5|iUDRCK_inferred_clock</td><td align="left">100.0 MHz</td><td align="left">13.4 MHz</td><td align="left">-32.246</td></tr>
<tr> <td align="left">PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0</td><td align="left">80.0 MHz</td><td align="left">55.0 MHz</td><td align="left">-5.671</td></tr>
<tr> <td align="left">PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0</td><td align="left">80.0 MHz</td><td align="left">55.1 MHz</td><td align="left">-5.638</td></tr>
<tr> <td align="left">PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R</td><td align="left">125.0 MHz</td><td align="left">116.7 MHz</td><td align="left">-0.228</td></tr>
<tr> <td align="left">PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop</td><td align="left">100.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0</td><td align="left">625.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1</td><td align="left">625.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2</td><td align="left">625.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3</td><td align="left">625.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV</td><td align="left">125.0 MHz</td><td align="left">230.3 MHz</td><td align="left">3.659</td></tr>
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV</td><td align="left">125.0 MHz</td><td align="left">225.1 MHz</td><td align="left">3.557</td></tr>
<tr> <td align="left">PHY_MDC_CLOCK</td><td align="left">2.9 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">REFCLK_P</td><td align="left">125.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">REF_CLK_0</td><td align="left">50.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>