abhishek/Ethernet-IP-Core
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head tail filter testing done

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abhishekpythons
2026-04-17 18:14:15 +05:30
parent e4b91625ea
commit a8e7c14f45
294 changed files with 209839 additions and 208687 deletions
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synthesis/synlog/top_premap.srr
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@@ -1,4 +1,4 @@
# Wed Apr 15 22:47:54 2026
# Fri Apr 17 08:31:43 2026
Copyright (C) 1994-2023 Synopsys, Inc.
@@ -19,7 +19,7 @@ Synopsys Microchip Technology Pre-mapping, Version map202309act, Build 395R, Bui
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB)
Done reading skeleton netlist (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 210MB peak: 210MB)
Done reading skeleton netlist (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 210MB peak: 210MB)
Reading constraint file: E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\synthesis.fdc
@L: E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top_scck.rpt
@@ -31,10 +31,10 @@ See clock summary report "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top
Design Input Complete (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 261MB peak: 261MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 261MB peak: 262MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 261MB peak: 262MB)
Start loading timing files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 265MB peak: 265MB)
Start loading timing files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 265MB peak: 265MB)
Finished loading timing files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 266MB peak: 267MB)
@@ -65,10 +65,10 @@ NConnInternalConnection caching is on
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop[1].buff_data[1][6:0] is being ignored due to limitations in architecture.
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop[0].buff_data[0][6:0] is being ignored due to limitations in architecture.
Starting HSTDM IP insertion (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 338MB peak: 338MB)
Starting HSTDM IP insertion (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 338MB peak: 338MB)
Finished HSTDM IP insertion (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 338MB peak: 339MB)
Finished HSTDM IP insertion (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 338MB peak: 339MB)
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":48:26:48:36|Tristate driver A_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net A_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":46:26:46:37|Tristate driver A_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net A_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
@@ -81,10 +81,10 @@ Finished HSTDM IP insertion (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:0
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":32:8:32:11|Tristate driver UTMS (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UTMS (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":31:8:31:13|Tristate driver UTRSTB (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UTRSTB (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
Started DisTri Cleanup (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 338MB peak: 339MB)
Started DisTri Cleanup (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 339MB peak: 339MB)
Finished DisTri Cleanup (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 338MB peak: 340MB)
Finished DisTri Cleanup (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 339MB peak: 340MB)
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":7090:6:7090:31|Removing instance gen_ext_sys_irq\[0\]\.gen_ext_sys_irq_bit\.u_miv_rv32_irq_reg_ext_sys (in view: work.miv_rv32_priv_irq_2s_0_0(verilog)) because it does not drive other instances.
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":7090:6:7090:31|Removing instance gen_ext_sys_irq\[1\]\.gen_ext_sys_irq_bit\.u_miv_rv32_irq_reg_ext_sys (in view: work.miv_rv32_priv_irq_2s_0_0(verilog)) because it does not drive other instances.
@@ -121,7 +121,7 @@ Finished DisTri Cleanup (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:0
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9245:6:9245:11|Removing sequential instance gen_gpr_ex_attbs_rd_ex\.gen_debug_gpr_rd_sel_pipeline\.de_ex_pipe_gpr_rs3_rd_sel_ex[5:0] (in view: work.miv_rv32_expipe_Z16(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
@N: FX1184 |Applying syn_allowed_resources blockrams=952 on top level netlist top
Finished netlist restructuring (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 348MB peak: 348MB)
Finished netlist restructuring (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 348MB peak: 348MB)
Some data will not be shown as it is part of encrypted module
@@ -133,7 +133,7 @@ Clock Summary
Level Clock Frequency Period Type Group Load
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
0 - REF_CLK_0 50.0 MHz 20.000 declared default_clkgroup 1
1 . PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 80.0 MHz 12.500 generated (from REF_CLK_0) (multiple) 5011
1 . PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 80.0 MHz 12.500 generated (from REF_CLK_0) (multiple) 4979
2 .. PHY_MDC_CLOCK 2.9 MHz 350.000 generated (from REF_CLK_0) default_clkgroup 0
0 - REFCLK_P 125.0 MHz 8.000 declared default_clkgroup 1
@@ -163,7 +163,7 @@ Clock Load Summary
Clock Load Pin Seq Example Seq Example Comb Example
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
REF_CLK_0 1 REF_CLK_0(port) PF_CCC_0_0.PF_CCC_0_0.pll_inst_0.REF_CLK_0 - -
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 5011 PF_CCC_0_0.PF_CCC_0_0.pll_inst_0.OUT0(PLL) PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1.B_CLK - PF_CCC_0_0.PF_CCC_0_0.clkint_0.I(BUFG)
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 4979 PF_CCC_0_0.PF_CCC_0_0.pll_inst_0.OUT0(PLL) PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C2.B_CLK - PF_CCC_0_0.PF_CCC_0_0.clkint_0.I(BUFG)
PHY_MDC_CLOCK 0 - - - -
REFCLK_P 1 REFCLK_P(port) PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.REF_CLK_0 - INBUF_DIFF_0.PADP(INBUF_DIFF)
@@ -191,7 +191,7 @@ PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop 2 PF_IOD_CDR
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.sap.
Starting constraint checker (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 333MB peak: 349MB)
Starting constraint checker (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:12s; Memory used current: 334MB peak: 349MB)
Encoding state machine mtx_state[5:0] (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog))
original code -> new code
@@ -263,11 +263,11 @@ original code -> new code
10 -> 10
11 -> 11
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core\rx_async.v":286:0:286:5|There are no possible illegal states for state machine rx_state[3:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
Encoding state machine state[1:0] (in view: work.fifo_to_tpsram_bridge(verilog))
Encoding state machine state[2:0] (in view: work.fifo_to_tpsram_bridge(verilog))
original code -> new code
00 -> 0
01 -> 1
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v":45:4:45:9|There are no possible illegal states for state machine state[1:0] (in view: work.fifo_to_tpsram_bridge(verilog)); safe FSM implementation is not required.
00 -> 00
01 -> 01
10 -> 10
Encoding state machine gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[15:0] (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog))
original code -> new code
0000 -> 0000000000000001
@@ -350,17 +350,17 @@ original code -> new code
11 -> 11
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\coredelaycode_tip\2.1.100\rtl\vlog\core\coredelaycode_tip.v":59:0:59:5|There are no possible illegal states for state machine state[3:0] (in view: work.COREDELAYCODE_TIP(verilog)); safe FSM implementation is not required.
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:11s; Memory used current: 341MB peak: 349MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 342MB peak: 349MB)
@W: MF511 |Found issues with constraints. Please check constraint checker report "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top_cck.rpt" .
Finished constraint checker (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:12s; Memory used current: 351MB peak: 365MB)
Finished constraint checker (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 351MB peak: 366MB)
Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:12s; Memory used current: 249MB peak: 365MB)
At Mapper Exit (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:14s; Memory used current: 249MB peak: 366MB)
Process took 0h:00m:13s realtime, 0h:00m:13s cputime
# Wed Apr 15 22:48:08 2026
Process took 0h:00m:15s realtime, 0h:00m:15s cputime
# Fri Apr 17 08:31:59 2026
###########################################################]