From 660d7555670e39ba3c998e4b8b1e3bc4ceb14682 Mon Sep 17 00:00:00 2001
From: abhishek <abhishekpythons@gmail.com>
Date: Mon, 13 Apr 2026 05:14:40 +0000
Subject: [PATCH] Add Design.md

---
 Design.md | 2 ++
 1 file changed, 2 insertions(+)
 create mode 100644 Design.md

diff --git a/Design.md b/Design.md
new file mode 100644
index 0000000..d4a7fda
--- /dev/null
+++ b/Design.md
@@ -0,0 +1,2 @@
+-  VSC8662 MAC interface dual port signals (Port 0 and Port1) RX/TX is connected on MSS SGMII
+Bank 5 (ref: (user manual)[https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/UserGuides/microchip_polarfire_soc_fpga_icicle_kit_user_guide_vb.pdf])