abhishek/Ethernet-IP-Core
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Update Design.md

Browse Source
This commit is contained in:
abhishek
2026-04-13 05:15:43 +00:00
parent 660d755567
commit 605b5da8ff
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
Design.md
View File

@@ -1,2 +1,2 @@
- VSC8662 MAC interface dual port signals (Port 0 and Port1) RX/TX is connected on MSS SGMII - VSC8662 MAC interface dual port signals (Port 0 and Port1) RX/TX is connected on MSS SGMII
Bank 5 (ref: (user manual)[https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/UserGuides/microchip_polarfire_soc_fpga_icicle_kit_user_guide_vb.pdf]) Bank 5 (ref: [user manual](https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/UserGuides/microchip_polarfire_soc_fpga_icicle_kit_user_guide_vb.pdf) )